High-Speed Flow-Based Classification on FPGA

Tristan Groleat (1, 2) , Sandrine Vaton (1, 2) , Matthieu Arzel (3, 4)

1 INFO - Département informatique
2 REOP - Réseaux d'opérateurs
3 ELEC - Département Electronique
4 Lab-STICC_TB_CACS_IAS

Analyzing the composition of Internet traffic has many applications nowadays, like tracking bandwidth consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Even though many flow-based classification methods, such as Support Vector Machines (SVM) have demonstrated their accuracy, few practical implementations of lightweight classifiers exist. We consider in this paper the design of a real-time SVM traffic classifier at hundreds of Gb/s to allow online detection of categories of applications. We also implement a high-speed flow reconstruction algorithm able to handle one million concurrent flows. The solution is based on the massive parallelism and low-level network interface access of FPGA boards. We find maximum supported bit rates up to 408 Gb/s for classification and up to 20 GB/s for flow reconstruction for the most challenging trace. Results are confirmed using a commercial Combov2 board with Analyzing the composition of Internet traffic has many applications nowadays, like tracking bandwidth consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Even though many flow-based classification methods, such as Support Vector Machines (SVM) have demonstrated their accuracy, few practical implementations of lightweight classifiers exist. We consider in this paper the design of a real-time SVM traffic classifier at hundreds of Gb/s to allow online detection of categories of applications. We also implement a high-speed flow reconstruction algorithm able to handle one million concurrent flows. The solution is based on the massive parallelism and low-level network interface access of FPGA boards. We find maximum supported bit rates up to 408 Gb/s for classification and up to 20 GB/s for flow reconstruction for the most challenging trace. Results are confirmed using a commercial Combov2 board with a Virtex 5 FPGA

Mots clés: Traffic classification; Flow reconstruction; SVM; FPGA prototype; FPGA

Domaines: Réseaux et télécommunications [cs.NI]

Tristan Groleat, Sandrine Vaton, Matthieu Arzel. High-Speed Flow-Based Classification on FPGA. International Journal of Network Management, 2014, 24 (4), pp.253-271. ⟨10.1002/nem.1863⟩. ⟨hal-01058333⟩